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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Bridge Core User’s Guide
Table 3. Register Map for Quad SPI-3 to SPI-4 LINK Layer Bridge Core (Continued)
Address: 0x8005
Name: DPRAM Read Provisioning Register 2
D7
D6
D5
D4
D3
D2
D1
D0
—
—
RSEL_2
Default value: Depends on con?guration. See Functional
Description section.
Description:
Mode: Read/Write
RSEL_2
Address: 0x8006
Selects virtual FIFO to be read during cycle 3 of 8.
Name: DPRAM Read Provisioning Register 3
D7
D6
D5
D4
D3
D2
D1
D0
—
—
RSEL_3
Default value: Depends on con?guration. See Functional
Description section.
Description:
RSEL_3
Address: 0x8007
Selects virtual FIFO to be read during cycle 4 of 8.
Name: DPRAM Read Provisioning Register 4
D7
D6
D5
D4
D3
D2
D1
D0
—
—
RSEL_4
Default value: Depends on con?guration. See Functional
Description section.
Description:
Mode: Read/Write
RSEL_4
Address: 0x8008
Selects virtual FIFO to be read during cycle 5 of 8.
Name: DPRAM Read Provisioning Register 5
D7
D6
D5
D4
D3
D2
D1
D0
—
—
RSEL_5
Default value: Depends on con?guration. See Functional
Description section.
Description:
Mode: Read/Write
RSEL_5
Address: 0x8009
Selects virtual FIFO to be read during cycle 6 of 8.
Name: DPRAM Read Provisioning Register 6
D7
D6
D5
D4
D3
D2
D1
D0
—
—
RSEL_6
Default value: Depends on con?guration. See Functional
Description section.
Description:
Mode: Read/Write
RSEL_6
Selects virtual FIFO to be read during cycle 7 of 8.
8
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